Underfill applications using film technology

ABSTRACT

A method and apparatus are provided for assembling a semiconductor package. The invention uses a thin release film placed over package components in a mold cavity. The release film is drawn down over the assembled components and envelops the assembled components with an airtight seal around at least three sides for assisting and defining the flow of encapsulant into empty space between components. A mold compound is flowed into the empty space, assisted by vacuum or air pressure at the airtight seal. The release film is pulled up and away from the assembled components, permitting encapsulant to flow into the remainder of the mold cavity.

FIELD OF THE INVENTION

The present invention relates to assembly and manufacture ofsemiconductor device packages and, more particularly, to a new techniquefor assembling semiconductor device packages using film technology.

BACKGROUND

Semiconductor devices, for example dynamic random access memory (DRAM)devices, are shrinking in the sense that smaller devices are beingmanufactured that are able to handle larger volumes of data at fasterdata transfer rates. As a result, semiconductor manufacturers are movingtoward chip-scale packages (CSP) for semiconductor components which havea small size and fine pitch wiring.

One exemplary CSP uses a chip-on-board (COB) construction whereby asemiconductor component, such as an integrated circuit (IC) chip, isattached to a base material, such as a substrate, with a conductiveadhesive material. The conductive adhesive material is interposedbetween and bonds the IC chip and the substrate at specified locationsin order to permit electrical connections between the chip andsubstrate. In addition, electrical traces or wiring patterns may beincluded in or on the substrate to permit the IC chip to connect withother external devices, for example a printed circuit board (PCB).

For example, in an exemplary COB package, solder balls may be used tobond and electrically connect the IC chip and the substrate. The solderballs may be placed at specified locations on the IC chip and/orsubstrate in order to form the desired electrical connections. Thesubstrate may be attached by leads, solder balls or other electricalconnectors to a PCB for use in an electronic system. Similar structuresmay be used in other types of semiconductor packages, such asboard-on-chip ball grid array (BOC-BGA), flip chip, wafer level CSP(WLCSP), and thin small outline packages (TSOP).

Because semiconductor manufacturers are continually under pressure toreduce the size of their packages, it is generally desirable to use asmall amount of adhesive between the IC chip and the substrate. Solderbumps (very small solder balls) may be used to bond the IC chip and thesubstrate, but the space between the IC chip and substrate is notcompletely filled with the adhesive, leaving a small amount of emptyspace adjacent the solder bumps. The resulting structure thus resemblesa “sandwich,” with solder bumps and empty space interposed between theIC chip and substrate. The empty space is usually filled with an“encapsulant,” or a mold compound to increase the reliability of thepackage. The process of filling the empty space with the encapsulant isknown as “underfill” of IC packages.

A problem arises in forming packages of small size, in that the gapbetween the IC chip and the substrate may be very small, such that theempty space may not be filled properly even when the encapsulant isapplied to fill the gap using high pressure or vacuum techniques. Anunfilled space between the IC chip and substrate is commonly known as a“void” and may lead to package reliability problems such as delaminationor cracks. For example, the manufacturing specification for the thinsmall outline package (TSOP) does not allow voids larger than 10 mils tobe present. However, for other packages the permissible voidspecification may be even more restrictive depending on the packagecharacteristics, such as package design, mold height, and materialsused. Post-encapsulation treatment may assist in eliminating the voids,but may increase the cycle time and production cost of the package.

Therefore, there is a strong need and desire for a technique forunderfilling IC packages that substantially eliminates voids withoutsignificantly increasing the cycle time or production cost of thesemiconductor packaging process.

SUMMARY

The invention provides a method and apparatus for producing asemiconductor package. The invention uses a thin release film placedover assembled components in a mold cavity, the assembled componentsincluding an integrated circuit (IC) chip, a substrate, and solder ballsor bumps interposed between the chip and substrate. The release film isdrawn down over and/or pressed against the assembled components assistedby at least one vacuum source, and pressure applied over the film usingair or mechanical means. The release film thus envelops the assembledcomponents and creates an airtight seal around at least three sides forinitially confining the flow of encapsulant into the area between thechip and substrate. A mold compound or encapsulant is then flowed intothe empty space between the chip and substrate, defined by vacuum andthe airtight seal created by the film. The release film is then pulledup and away from the assembled components, permitting encapsulant tothen flow into the remainder of the mold cavity.

In one embodiment, the mold cavity is formed to produce bare diesemiconductor packages, in which, after the release film is pulled up,the encapsulant is permitted to flow around the perimeter of the IC chipbut not over the top of the IC chip to form the semiconductor package.

In another embodiment, the mold cavity is formed for overmoldsemiconductor packages, in which, after the release film is pulled up,the encapsulant is permitted to flow around the perimeter and over thetop of the IC chip to form the semiconductor package.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of the invention willbecome more apparent from the detailed description of the exemplaryembodiments of the invention given below with reference to theaccompanying drawings in which:

FIG. 1 illustrates a side view of a semiconductor package being formedusing the apparatus and process methodologies of the invention;

FIG. 2 illustrates a top view of the semiconductor package of FIG. 1;

FIG. 3 illustrates a side view of the semiconductor package of FIG. 1 ata later stage of formation;

FIG. 4 illustrates a top view of the semiconductor package of FIG. 3;

FIG. 5 illustrates a side view of a semiconductor package being formedusing the apparatus and process methodologies of another embodiment ofthe invention;

FIG. 6 illustrates a side view of the semiconductor package of FIG. 5 ata later stage of formation;

FIG. 7 illustrates a view of the cross section VII—VII illustrated inFIG. 8;

FIG. 8 illustrates a top view of the semiconductor package of FIG. 5;

FIG. 9 is a block diagram illustrating the method of the invention; and

FIG. 10 illustrates a side view of a semiconductor package being formedusing the apparatus and process methodologies of an alternate embodimentof the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides a process and associated apparatus which uses athin release film to assist in the production of semiconductor packages.While the invention is described below with reference to a chip-on-board(COB) semiconductor package, including an integrated circuit (IC) chipattached to a substrate, it should be understood that the packagingmethodologies of the invention may be used with other types ofsemiconductor packages requiring the flow of a mold compound into smallgaps, for example chip-on-board ball grid array (COB-BGA), board-on-chipball grid array (BOC-BGA), flip chip, wafer level CSP (WLCSP), and thinsmall outline packages (TSOP).

Referring to FIG. 1, an exemplary packaging apparatus 20 is shownincluding a COB bare die semiconductor package during formation. A“sandwich” consisting of an integrated circuit (IC) chip 24, a substrate22, and solder bumps or solder balls 26 (gold bumps, coil springs and/orother interconnect means may also be used) is shown with the solderbumps 26 interposed between the IC chip 24 and the substrate 22. Thesandwich including the chip 24, substrate 22 and solder balls 26 ispositioned inside the mold cavitvy 32. A thin release film 30 is alsoplaced inside the mold cavity 32 covering the IC chip 24. The releasefilm 30 is held in place by attachments at the periphery 46, 48 of therelease film 30.

Release film handlers 47, 49 are positioned at two or more ends of thepackaging apparatus 20 which bring in a new fresh layer of film 30 atthe beginning of each packaging cycle. Each release film handler 47, 49tightens the film 30 with varying forces for specified periods of time,depending on the characteristics of the package being produced. At theend of the packaging cycle, the used film 30 may be removed anddiscarded by the release film handlers 47, 49. The release film handlers47, 49 may be programmable to function semi-automatically in cooperationwith a controller, for example a processor system. The release filmhandlers 47, 49 may also be manually operated or controlled.

It may be seen in FIG. 1 that the solder balls 26 do not completely fillthe gap between the chip 24 and the substrate 22, leaving a small amountof empty space 28 that may be filled with the encapsulant 29 (FIG. 3) toavoid delamination or cracks in the resulting package.

The mold cavity walls 50 define the shape of the final package. FIGS. 1and 5 show two exemplary embodiments of mold cavity configurations thatmay be used in the invention.

FIG. 1 illustrates an exemplary packaging apparatus for producing baredie packages. A bare die package is used to mount an IC chip 24 on asubstrate 22, leaving the top of the chip 24 exposed for furtherprocessing, external connection to other components, or simply todissipate heat. In the apparatus for producing bare die packages, themold cavity walls 50 are spaced slightly away from the film 30. Therelease film 30 is placed over the IC chip die 24 and no empty space ispresent between the film 30 and the top wall 50 of the mold cavity 32.

FIG. 5 illustrates an apparatus for producing overmold packages. Anovermold package is used to mount an IC chip 24 on a substrate 22 andencompass the IC chip 22 completely within the protective encapsulant29. In the apparatus for producing overmold packages, the mold cavitywalls 62 are formed to provide a specified amount of space (the“overmold space”) 65 over the IC chip die 24. The release film 30 isplaced over the IC chip die 24 in the overmold space 65, which separatesthe IC chip 24 and the top mold cavity walls 50. When the overmold spaceis filled with encapsulant 29 (FIG. 6), it provides a protectivecovering for the IC chip 24.

Referring back to FIG. 1, in operation the packaging apparatus 20 firstdraws the release film 30 down on the IC chip 24. FIG. 1 illustrates anexemplary system that uses air pressure and vacuum pressure to assistthe drawing down of the film 30 on the chip 24. Pressure is exerted onthe top side of the film 30 by forcing air into the first and second topvacuum/pressure ports 36, 38. Simultaneously, the film 30 is drawn downand air under the film 30 is removed by applying a vacuum using firstand second bottom vacuum ports 44, 42. As a result, the film 30 issucked down and stretched onto the chip-and-substrate sandwich,enveloping the chip 24 with an airtight “ring” surrounding the chip 24on at least three sides.

In drawing down the film 30, air pressure from the top is not required,and other means, for example mechanical pressure, may be used to similareffect. One exemplary mechanical means includes at least one arm thatpresses down on the film at a desired location to assist formation ofthe airtight “ring” before the mold is closed. An exemplary embodimentof the bare die apparatus 20′ employing mechanical arms 35, 37 inaccordance with the invention is shown in FIG. 10.

After the airtight “ring” is created around the chip 24 by the film 30,encapsulant 29 is permitted to flow into the empty space 28 between theIC chip 24 and the substrate 22. The encapsulant 29 flows from a source52 on one or more sides of the mold cavity 32.

FIG. 2 shows a top view of the package in the early stages of formation.The release film 30 is seen to be surrounding the IC chip 24 on at leastthree sides. Solder balls 26, hidden from the top view of FIG. 2, arepresent under the chip 24 but do not completely fill the space 28between the chip 24 and substrate 22. A source 52 supplies the moldcompound or encapsulant 29 that is permitted to flow through an entrance31 and between the substrate 22 and the IC chip 24 to fill the space 28.The vacuum pressure exerted by the bottom vacuum ports 42, 44 assiststhe underfill, or flow of the encapsulant 29 into the empty space 28.This operation is continued until the empty space is packed withencapsulant 29 sufficiently to eliminate or reduce the number and sizeof voids which might cause reliability problems.

After the underfill operation is completed, as shown in FIG. 3 thevacuum ports 42, 44 on the substrate side stop applying vacuum whichpermits a release of the film 30. Simultaneously, the vacuum ports 34,36, 38, 40 on the chip side are activated, pulling the film 30 up andaway from the substrate 22 and the chip 24. When the film 30 is releasedfrom the chip 24, the film 30 takes the shape of the mold cavity 32,thus permitting the encapsulant 29 to flow around the periphery of theIC chip 24. The resulting package takes the shape of the mold cavitywalls 50. As illustrated in FIG. 4, the resulting package includes tieIC chip 24 surrounded on four sides by the encapsulant 29. FIG. 4 showsthe top view of the package after the encapsulant 29 has flowed from thesource 52 completely around the periphery of the IC chip 24.

Although the packaging cycle is described for release of the usedrelease film 30 from the IC chip 24 as an act separate from flow of theencapsulant 29, this is not required. The flow of the encapsulant 29 maybe uninterrupted during the packaging cycle, i.e., the film 30 isreleased from the IC chip 24 during flow of the encapsulant 29.Alternatively, the flow of the encapsulant 29 into the mold cavity 32may be interrupted to permit the release film 30 to be released from theIC chip 24. For example, the flow of the encapsulant 29 into the emptyspace 28 between the substrate 22 and the IC chip 24 may be stopped, thefilm 30 may be released from the IC chip 24, and then flow of theencapsulant 29 may resume to fill the remainder of the mold cavity 32.

At the end of the process, the package is formed with the shape and sizeof the mold cavity 32, except that the package dimensions are determinedby the mold cavity walls 50 less the thickness of the film 30. Incontrast, using a conventional process, the dimensions of the packageare determined only by the dimensions of the mold cavity. Moreimportantly, the underfill area is substantially filled with theassistance of the release film and applied vacuum.

Following its use in the packaging operation, the film 30 is selfreleased from the package and removed from the mold cavity 32 fordisposal or recycling. For the next cycle of the packaging operation, afresh layer of the release film 30 is obtained and positioned in themold cavity 32.

The release film 30 may be any flexible, thin film compatible withsemiconductor processing conditions. Typical desired properties mayinclude: low flammability; specific electrical and mechanical properties(e.g., good elongation); very good resistance to solvents and chemicals;extremely high resistance to weathering; nonstick characteristics; goodstress cracking resistance. One exemplary release film 30 that may beused is a melt processable fluoroplastic, consisting mainly ofalternating tetrafluoroethylene and ethylene monomer units, that is ableto withstand temperatures ranging from about −200 to 150 degrees Celsiusand short term exposure (e.g., 6 to 8 hours or less) to temperatures upto 230 degrees Celsius. Two release films of this type that may be usedare the Hostaflon ET6235J and Hostaflon ET6210J.

The mold compound or encapsulant 29 may be any encapsulation compoundthat is used in the molding, dispensing, or screen printing of ICpackages. Typical properties of an appropriate encapsulant materialinclude: low warpage; good adhesion properties with respect to the die,substrate, die attached tape and paste; good releasability from the molddie and the release film; ability to fill small gaps; good flowability;low stress; low water absorption; good reliability performance; goodflexural strength; good dielectric stability; good thermal stability;low alpha emission; and low flammability.

FIG. 5 illustrates another exemplary packaging apparatus 60 including aCOB overmold semiconductor package during formation. A “sandwich”consisting of an integrated circuit (IC) chip 24, a substrate 22, andsolder bumps or solder balls 26 (gold bumps, coil springs and/or otherinterconnect means may also be used) is shown with the solder balls 26interposed between the IC chip 24 and the substrate 22. The sandwichincluding the chip 24, substrate 22 and solder balls 26 is positionedinside the overmold mold cavity 64. A thin release film 30 is alsoplaced inside the mold cavity 64 covering the IC chip 24. The releasefilm 30 is held in place by attachments at the periphery 46, 48 of therelease film 30.

In operation, the overmold packaging apparatus 60 is operated in amanner similar to the operations of the bare die apparatus 20. Therelease film 30 is drawn down to create of an airtight ring around theIC chip 24 (FIG. 8), the encapsulant 29 is flowed into the empty space28 between the chip 24 and the substrate 22 assisted by vacuum (FIG. 5),and the release film is pulled up and away from the chip 24 to permitthe encapsulant 29 to flow around the periphery of the chip 24 (FIG. 6).However, in contrast to the bare die apparatus illustrated in FIGS. 1-4,the overmold apparatus 60 allows the encapsulant 29 to flow over the ICchip 24 into the overmold space 65 as well, as illustrated in FIG. 6.

FIG. 8 illustrates a top view of the exemplary apparatus 60 prior toflow of the encapsulant 29. The release film 30 is seen to besurrounding the IC chip 24 on at least three sides. Solder balls 26(hidden lines in the top view of FIG. 8) are present under the chip 24.A source 52 supplies the mold compound or encapsulant 29 that ispermitted to flow through a runner 82 and a gate 84 before it reachesthe empty space 28 between the substrate 22 and the IC chip 24.

FIG. 7 illustrates a side view of the cross section VII—VII shown inFIG. 8, showing the exemplary packaging apparatus 60 prior to flow ofthe encapsulant 29. The encapsulant 29 enters the mold cavity 64 via therunner 82 and the gate 84. The bottom vacuum port 80 on the oppositeside of the gate 84 and runner 82 is turned on to create the airtightring around the chip 24 via the film 30. The top vacuum port 72 nearestthe runner 82 is also turned on to ensure that the flow of theencapsulant 28 through the gate 84 and runner 82 is not impeded by therelease film 30. Top vacuum/pressure ports 74, 76 may be used to exertpressure on the release film 30 from above to assist the formation ofthe airtight ring surrounding the chip 24. As noted, the encapsulant 29then is flowed into the empty space 28 between the chip 24 and thesubstrate 22, and the release film 30 is pulled up and away from thechip 24 to permit the encapsulant 29 to flow around the periphery of thechip 24 and into the overmold space 65.

FIG. 9 illustrates an exemplary embodiment of the method of theinvention, applicable to each of the exemplary structures 20, 60previously described with reference to FIGS. 1-4 and 5-8, respectively.The “sandwich” composed of the substrate 22, the IC chip 24, and thesolder balls 26 is assembled in the mold cavity in method segment 90.The release film 30 is drawn down on the IC chip 24 in method segment 92as noted, i.e., assisted by appropriate vacuum and/or air pressureapplied using the ports 34, 36, 38, 40, 42, 44 on the top and bottom ofthe apparatus. The release film 30 creates an airtight “ring” around atleast three sides of the chip 24 to define areas for the flow of theencapsulant 29 into the empty space 28 between the chip 24 and thesubstrate 22. In method segment 94, the encapsulant 29 flows into thisempty space 28, assisted by the vacuum created by the lower vacuum ports42, 44 and the release film 30. After the empty space 28 issubstantially filled with encapsulant 29, the film 30 is pulled up andaway from the chip 24, for example using the top and bottom vacuum ports34, 36, 38, 40, 42, 44 in method segment 96. When pulled away from thechip 24, the film 30 takes the shape of the mold cavity walls 50. Thusthe encapsulant 29 is permitted to flow into the remainder of the moldcavity 32, including around the perimeter of the chip 24.

The method and apparatus described provide a packaging methodology thatallows substantially all of the empty space between a substrate and anintegrated circuit chip not occupied by solder bumps or balls to befilled with encapsulant during underfill operations. The release filmused in the invention creates an airtight ring around several sides ofthe chip and the empty space being filled, improving the flow of theencapsulant into small gaps. In this way, even very small voids may beeliminated in the encapsulant between the chip and the substrate,improving the reliability characteristics of the resulting package.

While the invention has been described and illustrated with reference tospecific exemplary embodiments, it should be understood that manymodifications and substitutions can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as limited by the foregoing description but is onlylimited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of assembling a semiconductor package,comprising: forming an assembly of an integrated circuit chip on asubstrate with spaced electrical connectors connecting and disposedbetween said integrated circuit chip and said substrate; placing saidassembly within a mold cavity and providing a release film over at leasta portion of said substrate and around at least three sides of saidintegrated circuit chip; causing the release film to be drawn down oversaid at least three sides of said integrated circuit chip and saidportion of said substrate; flowing encapsulant into empty space betweensaid integrated circuit chip and said substrate; causing the releasefilm to be released from said at least three sides of said integratedcircuit chip; and flowing encapsulant into an unfilled remainder of saidmold cavity.
 2. The method of claim 1, wherein said electricalconnectors are solder bumps.
 3. The method of claim 1, wherein saidelectrical connectors are solder balls.
 4. The method of claim 1,wherein said causing the release film to be drawn down includes applyinga vacuum to pull the release film down over at least said portion ofsaid substrate.
 5. The method of claim 1, wherein said causing therelease film to be drawn down includes applying air pressure to therelease film forcing it into contact with at least said portion of saidsubstrate.
 6. The method of claim 1, wherein causing said release filmto be drawn down includes using at least one mechanical arm to exertpressure on the release film.
 7. The method of claim 1, wherein causingsaid release film to be released includes applying a vacuum to pull therelease film away from the integrated circuit and the substrate.
 8. Themethod of claim 1, wherein the mold cavity is formed such that there isno empty space between the release film and a top wall of the moldcavity.
 9. The method of claim 1, wherein the mold cavity is formed suchthat an overmold space is present between the integrated circuit chipand a top wall of the mold cavity.
 10. The method of claim 1, whereinsaid flowing of said encapsulant into said empty space includes applyinga vacuum to assist the flow of said encapsulant into said empty space.11. The method of claim 1, wherein said flowing of said encapsulant intosaid empty space includes applying air pressure to assist the flow ofsaid encapsulant into said empty space.
 12. The method of claim 1,wherein during said flowing of said encapsulant into said empty space,said encapsulant fills substantially all of said empty space betweensaid integrated circuit chip and said substrate.
 13. The method of claim1, wherein said flowing of said encapsulant into said unfilled remainderincludes flowing encapsulant around a perimeter of said integratedcircuit chip.
 14. The method of claim 1, wherein said flowing of saidencapsulant into said unfilled remainder includes flowing encapsulantover an upper surface of said integrated circuit chip.
 15. The method ofclaim 1, wherein during said flowing of said encapsulant into saidunfilled remainder, said encapsulant fills substantially all of saidmold cavity previously unfilled.
 16. The method of claim 1, whereinduring said causing of said release film to be drawn down, said releasefilm substantially envelops said integrated circuit chip to create anairtight seal around at least three sides of said empty space betweensaid integrated circuit chip and said substrate.
 17. The method of claim1, further comprising removing said release film from said mold cavityfollowing said flowing of said encapsulant into said unfilled remainder.18. The method of claim 1, wherein said causing said release film to bereleased is performed during said flowing of said encapsulant.
 19. Themethod of claim 1, wherein said causing said release film to be releasedis performed prior to said flowing of said encapsulant into saidunfilled remainder.
 20. The method of claim 1, wherein said flowing ofsaid encapsulant into said empty space ceases, said release film isreleased from said at least three sides of said integrated circuit chip,and said flowing of said encapsulant resumes to flow into said unfilledremainder.
 21. A method of assembling a bare die semiconductor package,comprising: forming an assembly of an integrated circuit chip on asubstrate with spaced electrical connectors connecting and disposedbetween said integrated circuit chip and said substrate; placing saidassembly within a mold cavity and providing a release film over at leasta portion of said substrate and around at least three sides of saidintegrated circuit chip, wherein said mold cavity is formed with noempty space between a top wall of said mold cavity and said releasefilm; causing the release film to be drawn down over said at least threesides of said integrated circuit chip and said portion of saidsubstrate; flowing encapsulant into empty space between said integratedcircuit chip and said substrate; causing the release film to be releasedfrom said at least three sides of said integrated circuit chip; andflowing encapsulant into an unfilled remainder of said mold cavity. 22.A method of assembling an overmold semiconductor package, comprising:forming an assembly of an integrated circuit chip on a substrate withspaced electrical connectors connecting and disposed between saidintegrated circuit chip and said substrate; placing said assembly withina mold cavity and providing a release film over at least a portion ofsaid substrate and around at least three sides of said integratedcircuit chip, wherein said mold cavity is formed having an overmoldspace between a top wall of said mold cavity and said release film;causing the release film to be drawn down over said at least three sidesof said integrated circuit chip and said portion of said substrate;flowing encapsulant into empty space between said integrated circuitchip and said substrate; causing the release film to be released fromsaid at least three sides of said integrated circuit chip; and flowingencapsulant into an unfilled remainder of said mold cavity, includingsaid overmold space.
 23. An apparatus for filling gaps in integratedcircuit packages, comprising: a mold cavity; a release film providedover at least a portion of a substrate and around at least three sidesof an integrated circuit chip placed within said mold cavity; at leastone release film handler that inserts said release film into said moldcavity and removes said release film from said mold cavity; a pluralityof spaced electrical connectors connecting and disposed between saidintegrated circuit chip and said substrate; and at least one entrance insaid mold cavity that permits flow of an encapsulant material into saidmold cavity and between said integrated circuit chip and said substrate.24. The apparatus of claim 23, wherein said electrical connectors aresolder bumps.
 25. The apparatus of claim 23, wherein said electricalconnectors are solder balls.
 26. The apparatus of claim 23, wherein themold cavity is formed such that there is no empty space between therelease film and a top wall of the mold cavity.
 27. The apparatus ofclaim 23, wherein the mold cavity is formed such that an overmold spaceis present between the integrated circuit chip and a top wall of themold cavity.
 28. The apparatus of claim 23, further comprising upper andlower vacuum ports that assist flow of said encapsulant into said moldcavity and between said substrate and said integrated circuit chip. 29.The apparatus of claim 23, further comprising at least one air pressureport that assists flow of said encapsulant into said mold cavity andbetween said substrate and said integrated circuit chip.
 30. Theapparatus of claim 23, further comprising at least one air pressure portthat assists in pressing the release film down over the integratedcircuit chip and substrate.
 31. The apparatus of claim 23, furthercomprising at least one mechanical arm that assists in pressing therelease film down over the integrated circuit chip and substrate. 32.The apparatus of claim 23, wherein said release film substantiallyenvelops said integrated circuit chip to create an airtight seal aroundat least three sides of said electrical connectors between saidintegrated circuit chip and said substrate.
 33. An apparatus for fillinggaps in bare die semiconductor packages, comprising: a mold cavityhaving walls, said walls formed such that a space is present between atop wall of said mold cavity and an integrated circuit chip placedwithin said mold cavity; a release film provided within said moldcavity, around at least three sides of said integrated circuit chip andover at least a portion of a substrate, said release film substantiallyfilling said space; at least one release film handler that inserts saidrelease film into said mold cavity and removes said release film fromsaid mold cavity; a plurality of spaced electrical connectors connectingand disposed between said integrated circuit chip and said substrate;and at least one entrance in said mold cavity that permits flow of anencapsulant material into said mold cavity and between said integratedcircuit chip and said substrate.
 34. An apparatus as in claim 33,wherein said apparatus is for filling gaps in COB packages.
 35. Anapparatus as in claim 33, wherein said apparatus is for filling gaps inflip chip packages.
 36. An apparatus for filling gaps in overmoldsemiconductor packages, comprising: a mold cavity having walls, saidwalls formed to create an overmold space between a top wall of said moldcavity and an integrated circuit chip placed within said mold cavity; arelease film provided within said mold cavity, over at least a portionof a substrate and around at least three sides of said integratedcircuit chip; at least one release film handler that inserts saidrelease film into said mold cavity and removes said release film fromsaid mold cavity; a plurality of spaced electrical connectors connectingand disposed between said integrated circuit chip and said substrate;and at least one entrance in said mold cavity that permits flow of anencapsulant material into said mold cavity and between said integratedcircuit chip and said substrate.
 37. An apparatus as in claim 36,wherein said apparatus is for filling gaps in COB packages.
 38. Anapparatus as in claim 36, wherein said apparatus is for filling gaps inflip chip packages.